1. Field of the Invention
The present invention relates to non-volatile memory devices, and multi-page program, read and copyback program method thereof. More specifically, the present invention relates to non-volatile memory devices having a multi-plane structure, and multi-page program, read and copyback program method thereof.
2. Discussion of Related Art
In the case of NAND-type flash memory devices, the program speed is very slow, i.e., about several hundreds of μs. To improve the program throughput becomes an important parameter representing the performance of chips. In order to enhance the program throughput, various program operation methods such as a cache program and a multi-page program have been proposed. In the case of the cache program, while data are programmed into a cell, next data are previously stored in a page buffer. The cache program method has, however, a lower efficiency as the program time of the cell is higher than the data input time.
FIG. 1 is a block diagram of a conventional NAND-type flash memory device that performs a multi-page program operation in the multi-plane structure.
Referring to FIG. 1, the NAND-type flash memory device includes N number of planes PN<0> to PN<n>. Each of the planes PN<0> to PN<n> has J number of memory cell blocks MB<0> to MB<j>. Each of the memory cell blocks MB<0> to MB<j> has M number of pagers PG<0> to PG<m>, which are controlled by M number of word lines WL0 to WLm, respectively.
In FIG. 1, to K number of page buffers PB<0> to PB<k> in each of the planes PN<0> to PN<n> are sequentially input K number of data. After the data are sequentially input, a program operation ({circle around (1)}) and a program verify operation ({circle around (2)}) are performed on only even memory cells (or odd memory cells connected to odd bit lines BLo), which are connected to one word line (e.g., WL1) within the planes PN<0> to PN<n> and to even bit lines BLe during a program time.
FIG. 2 shows one plane structure in FIG. 1.
Referring to FIG. 2, one word line (e.g., WL1) is connected to the gates of cells MC1 connected to the even bit line BLe and cells MC1′ connected to the odd bit line BLo. One page buffer (e.g., PB<0>) is connected to the even bit line BLe and the odd bit line BLo through a sensing line SO. The page buffer (e.g., PB<0>) is connected to the even bit line BLe when an even bit line select signal BSLe is activated, and is connected to the odd bit line BLo when an odd bit line select signal BSLo is activated.
This NAND-type flash memory device employs a bit line shielding scheme in which the even bit line BLe and the odd bit line BLo are divided in order to prevent a read fail incurred by bit line coupling. The bit line shielding scheme uses the odd bit line BLo as a shielding bit line when reading a memory cell connected to the even bit line BLe.
In the multi-page program method of the NAND-type flash memory device having the above-described N-plane structure, however, data can be programmed into only the memory cells MC1 (or cells MC1′ connected to BLe), which are connected to the even bit line BLe within the page PG<1> selected by one word line (for example, WL1).